The level of functionality of electric devices such as portable information terminal devices such as cellular phones, computers and peripheral equipment thereof, and various home information products has been rapidly increasing. Accordingly, circuit boards that are carried in such electric devices are required to have an even higher density of electric circuits. Methods that can form accurately the wiring of electric circuits that is decreased in line width and line spacing (width of portions between the adjacent electric circuits) are needed to meet such a demand for increased density of circuits. In circuit wirings of increased density, short circuiting or migration between the wirings can easily occur.
A method for forming an electric circuit on an insulative substrate by a subtractive method or an additive method is known as a method of producing a circuit board. With the subtractive process, an electric circuit is formed by removing (subtractive) a metal foil outside a portion where an electric circuit is wished to be formed on the surface of a metal foil stretched laminate. With the additive processes, an electric circuit is formed by conducting electroless plating only on the portion where a circuit is wished to be formed on an insulative substrate.
In the subtractive method, the metal foil is left only in the portion where the electric circuit is wished to be formed (circuit formation portion) and removed from other portions by etching the thick-film metal foil. With such a method, the metal from the removed portions is wasted and therefore the production cost is disadvantageously high. With the additive method, metal wiring can be formed by electroless plating only on the portions where the electric circuit is wished to be formed. Therefore, no metal is wasted and natural resources can be saved. These reasons also make the additive method an advantageous circuit formation method.
A method for forming an electric circuit including metal wirings by a full additive method, which is one of the typical conventional additive methods, will be described below with reference to FIGS. 5A to 5E. FIGS. 5A to 5E are schematic cross-sectional views illustrating steps of forming a metal wiring by the conventional full additive method.
First, as shown in FIG. 5A, a plating catalyst 102 is deposited to the surface of an insulative substrate 100 having a through hole 101 formed therein. The surface of the insulative substrate 100 has been roughened in advance. Then, as shown in FIG. 5B, a photoresist layer 103 is formed on the insulative substrate 100 to which the plating catalyst 102 has been deposited. Then, as shown in FIG. 5C, the photoresist layer 103 is exposed via a photomask 110 in which a predetermined circuit pattern has been formed. Then, as shown in FIG. 5D, the exposed photoresist layer 103 is developed and a circuit pattern 104 is formed. Then, as shown in FIG. 5E, a metal wiring 105 is formed by performing electroless plating such as electroless copper plating on the surface of the circuit pattern 104 that has been formed by development and the inner wall surface of the through hole 101. By performing the abovementioned steps, a circuit including the metal wiring 105 is formed on the insulative substrate 100.
In the above-described conventional additive method, the plating catalyst 102 is deposited to the entire surface of the insulative substrate 100. As a result, the following problem is encountered. Thus, when the photoresist layer 103 is developed with high accuracy, a plating film can be formed only on the portion that is not protected by the photoresist. However, when the photoresist layer 103 is not developed with high accuracy, an unnecessary plating portion 106 sometimes remains on the portion where the plating film is not wished to be formed, as shown in FIG. 6. Such a result is due to the deposit of the plating catalyst 102 to the entire surface of the insulative substrate 100. The unnecessary plating portion 106 causes short circuiting or migration between the adjacent circuits. Such short circuiting or migration easier occurs when a circuit with small line width and line spacing is formed. FIG. 6 is a schematic cross-sectional view illustrating the contour shape of the circuit formed by the conventional full additive method.
Examples of manufacturing methods that differ from the above-described method of producing a circuit substrate are described in Patent Document 1 and Patent Document 2.
Patent Document 1 discloses the following method as another additive method.
First, a solvent-soluble first photosensitive resin layer and an alkali-soluble second photosensitive resin layer are formed on an insulating substrate (insulating base material). Then, the first and second photosensitive resin layers are exposed via a photomask having a predetermined circuit pattern. Then, the first and second photosensitive resin layers are developed. A catalyst is then caused to be adsorbed by the entire surface including the recess formed by the development, and then only the unnecessary catalyst is removed by dissolving the alkali-soluble second photosensitive resin layer with an alkali solution. A circuit is then accurately formed by electroless plating only on the portion where the catalyst is present.
Patent Document 2 discloses the following method.
First, a resin protective film is coated on an insulative substrate (insulating base material) (first step). Then, a groove and a through hole corresponding to a wiring pattern are individually or simultaneously delineated and formed by mechanical processing or laser beam irradiation on the insulating substrate coated with the protective film (second step). An activation layer is then formed over the entire surface of the insulating substrate (third step). The protective film is then peeled off, the activation layer present on the insulating substrate is removed, and the activation layer is left only on the inner wall surface of the groove and through hole (fourth step). The insulating substrate is then plated without using a plating protective film and an electrically conductive layer is selectively formed only on the inner wall surface of the activated groove and through hole (fifth step).
Patent Document 2 also indicates that a thermosetting resin is coated as the protective film on the insulating substrate and thermally cured and then the protective film and the insulating substrate are machined according to the predetermined wiring pattern and that the thermosetting resin present on the surface of the insulating substrate is removed with a solvent (Patent Document 2, second page, lower left column, line 16 to lower right column, line 11).
Patent Document 1: Japanese Patent Application Publication No. S57-134996
Patent Document 2: Japanese Patent Application Publication No. S58-186994